The present invention relates to integrated circuits. It finds particular application in conjunction with integrated circuits which provide high voltage power to electric motors and other inductive loads and will be described with particular reference thereto. However, it is to be appreciated that the present invention will also find application in conjunction with integrated circuits for other high and low voltage applications with inductive and non-inductive loads.
Heretofore, transistors, SCRs, diodes, and other discrete solid state components have commonly been used to control electric motors and other large inductive loads. One drawback of using discrete components has been that they are relatively space inefficient. Another drawback resides in high manufacturing and labor costs.
To overcome the drawbacks of discrete components, the power and control components have been fabricated in a single integrated circuit with a common substrate. Transistors and SCRs which provide power to inductive loads typically have a PN junction which becomes forward-biased, e.g., an NPN collector or a MOSFET drain is biased negatively. A high level of minority carriers are injected by the forward-biased junction. Under these conditions, a parasitic transistor or SCR formed with other doped regions on the common substrate becomes active.
One solution to minimize the effect of the parasitic device has been to create a moat or guard ring around the power components. That is, the minority carrier injector is surrounded by epitaxial and deep regions of the opposite dopant type. The moat is connected to ground. In this manner, some of the injected minority carriers or stray substrate currents are shunted to ground, limiting the interaction of the forward-biased node with other nodes that form parasitic transistors or SCRs. (See, for example, "Power Integrated Circuits: Physics, Design and Applications", Paolo Antognetti, Page 4 20, (1986).) Although grounded moats can reduce the parasitic currents by two or three orders of magnitude below the injected currents, significant parasitic currents still remain.
The present invention contemplates a new and improved minority carrier protection scheme for integrated circuits relying at least partially on junction isolation.